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Final Electrical Specifications
LTC3723-1/LTC3723-2 Synchronous Push-Pull PWM Controllers
October 2003
FEATURES
s s s
DESCRIPTIO
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s s s s s
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High Efficiency Synchronous Push-Pull PWM 1.5A Sink, 1A Source Output Drivers Adjustable Push-Pull Dead-Time and Synchronous Timing Adjustable System Undervoltage Lockout and Hysteresis Adjustable Leading Edge Blanking Low Start-Up and Quiescent Currents Current Mode (LTC3723-1) and Voltage Mode (LTC3723-2) Operation Single Resistor Slope Compensation VCC UVLO and 25mA Shunt Regulator Programmable Fixed Frequency Operation to 1MHz 50mA Synchronous Output Drivers Soft-Start, Cycle-by-Cycle Current Limiting and Hiccup Mode Short-Circuit Protection 5V, 15mA Low Dropout Regulator Available in 16-Pin SSOP Package
The LTC(R)3723-1/LTC3723-2 synchronous push-pull PWM controllers provide all of the control and protection functions necessary for compact and highly efficient, isolated power converters. High integration minimizes external component count, while preserving design flexibility. The robust push-pull output stages switch at half the oscillator frequency. Dead-time is independently programmed with an external resistor. Synchronous rectifier timing is adjustable to optimize efficiency. A UVLO program input provides precise system turn-on and turn off voltages. The LTC3723-1 features peak current mode control with programmable slope compensation and leading edge blanking, while the LTC3723-2 employs voltage mode control with voltage feedforward capability. The LTC3723-1/LTC3723-2 feature extremely low operating and start-up currents. Both devices provide reliable short-circuit and overtemperature protection. The LTC3723-1/LTC3723-2 are offered in a 16-pin SSOP package.
, LTC and LT are registered trademarks of Linear Technology Corporation.
APPLICATIO S
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Telecommunications, Infrastructure Power Systems Distributed Power Architectures
TYPICAL APPLICATIO
VIN 36V TO 72V 300k 51k
Isolated 36V to 72V DC to 12V/15A Push-Pull Converter
2H VOUT 12V/15A
UVLO 100k FROM AUXILIARY WINDING 22F 20k VREF 1F CT 330pF 20k RLEB DPRG 30k SPRG VCC
DRVA DRVB CS 330
IRF1310N IRF1310N * 0.05 1F * *
1F 1/2 LTC1693
SDRA SDRB VREF LTC3723-1 1F 3.3k VOUT 1F
1/2 LTC1693
SS 3.9nF
COMP FB GND
470
372312 TA01
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
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2H 8k IRL3103 25k 470F IRL3103 VOUT V+ COLL COMP LT1431 10k 1F RTOP RREF RMID GND-F GND-S
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372312i
1
LTC3723-1/LTC3723-2
ABSOLUTE
AXI U RATI GS
VCC to GND (Low Impedance Source) .......- 0.3V to 10V (Chip Self-Regulates at 10.3V) UVLO to GND ............................................. - 0.3V to VCC All Other Pins to GND (Low Impedance Source) .........................- 0.3V to 5.5V VCC (Current Fed) ................................................. 40mA
PACKAGE/ORDER I FOR ATIO
TOP VIEW VREF SDRB SDRA DRVB VCC DRVA GND CT 1 2 3 4 5 6 7 8 16 SPRG 15 UVLO 14 SS 13 FB 12 RLEB 11 COMP 10 CS 9 DPRG
ORDER PART NUMBER LTC3723EGN-1
GN PART MARKING 37231
GN PACKAGE 16-LEAD PLASTIC SSOP
TJMAX = 125C, JA = 100C/W
Consult LTC Marketing for parts specified with wider operating temperature ranges.
The q denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VCC = 9.5V unless otherwise noted.
SYMBOL Input Supply VCCUV VCCHY ICCST ICCRN VSHUNT RSHUNT SUVLO SHYST VCC Undervoltage Lockout VCC UVLO Hysteresis Start-Up Current Operating Current Shunt Regulator Voltage Shunt Resistance System UVLO Threshold System UVLO Hysteresis Current Measured on VCC Measured on VCC VCC = VUVLO - 0.3V No Load on Outputs Current into VCC = 10mA Current into VCC = 10mA to 17mA Measured on UVLO Pin, 10mA into VCC Current Flows Out of UVLO Pin, 10mA into VCC 4.8 8.5
q
ELECTRICAL CHARACTERISTICS
PARAMETER
CONDITIONS
2
U
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W
WW U
W
(Note 1)
VREF Output Current ............................... Self-Regulated Operating Temperature (Notes 5,6) LTC3723E ........................................... - 40C to 85C Storage Temperature Range ................. - 65C to 125C Lead Temperature (Soldering, 10sec)................... 300C
TOP VIEW VREF SDRB SDRA DRVB VCC DRVA GND CT 1 2 3 4 5 6 7 8 16 SPRG 15 UVLO 14 SS 13 FB 12 DPRG 11 COMP 10 CS 9 RAMP
ORDER PART NUMBER LTC3723EGN-2
GN PART MARKING 37232
GN PACKAGE 16-LEAD PLASTIC SSOP
TJMAX = 125C, JA = 100C/W
MIN
TYP 10.25
MAX 10.7 230 6 10.8 3.5 5.2 11.5
UNITS V V A mA V V A
3.8
4.2 145 3 10.3 1.4 5.0 10
372312i
LTC3723-1/LTC3723-2
The q denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VCC = 9.5V unless otherwise noted.
SYMBOL ROS IRMP ISLP DCMAX DCMIN DTADJ Oscillator OSCI OSCT OSCV VFB FBI AVOL IIB VOH VOL ISOURCE ISINK Reference VREF REFLD REFLN REFTV REFSC DRVH(x) DRVL(x) RDH(x) RDL(x) TDR(x) TDF(x) Initial Accuracy Load Regulation Line Regulation Total Variation Short-Circuit Current Output High Voltage Output Low Voltage Pull-Up Resistance Pull-Down Resistance Rise-Time Fall-Time TA = 25C, Measured on VREF Load on VREF = 100A to 5mA VCC = 6.5V to 9.5V Line, Load and Temperature VREF Shorted to GND IOUT(x) = -100mA IOUT(x) = 100mA IOUT(x) = -10mA to -100mA IOUT(x) = -10mA to -100mA COUT(x) = 1nF COUT(x) = 1nF
q
ELECTRICAL CHARACTERISTICS
PARAMETER Ramp Offset Voltage Ramp Discharge Current Slope Compensation Current Maximum Duty Cycle Minimum Duty Cycle Dead-Time Initial Accuracy VCC Variation CT Ramp Amplitude FB Input Voltage FB Input Range Open-Loop Gain Input Bias Current Output High Output Low Output Source Current Output Sink Current
CONDITIONS Measured on COMP, RAMP = 0V RAMP = 1V, COMP = 0V, CT = 4V, 3723-1 Only Measured on CS, CT = 1V, 3723-1 Only CT = 2.25V COMP = 4.5V COMP = 0V
q q
MIN
TYP 0.65 50 30 68
MAX
UNITS V mA A A
Pulse Width Modulator
47
48.2 0 130
50
% % ns
TA = 25C, CT = 270pF VCC = 6.5V to 9.5V, Overtemperature Measured on CT COMP = 2.5V, (Note 3) Measured on FB, (Note 4) COMP = 1V to 3V, (Note 3) COMP = 2.5V, (Note 3) Load on COMP = -100A Load on COMP = 100A COMP = 2.5V COMP = 2.5V
q
220 -3
250 2.35
280 3
kHz % V
Error Amplifier 1.172 - 0.3 70 4.7 400 2 4.925 90 5 4.92 0.27 700 5 5.00 2 1 4.900 18 9 5.000 30 9.2 0.17 2.9 1.7 10 10 0.25 4 2.5 5.075 15 10 5.100 45 0.5 50 1.2 1.22 2.5 V V dB nA V V A mA V mV mV V mA V V ns ns
Push-Pull Outputs
372312i
3
LTC3723-1/LTC3723-2
The q denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VCC = 9.5V unless otherwise noted.
SYMBOL OUTH(x) OUTL(x) RHI(x) RLO(x) TR(x) TF(x) CLPP CLSD CLDEL SSI SSR FLT PARAMETER Output High Voltage Output Low Voltage Pull-Up Resistance Pull-Down Resistance Rise-Time Fall-Time Pulse by Pulse Current Limit Threshold Shutdown Current Limit Threshold Current Limit Delay to Output Soft-Start Current Soft-Start Reset Threshold Fault Reset Threshold CONDITIONS IOUT(x) = -30mA IOUT(x) = 30mA IOUT(x) = -10mA to -30mA IOUT(x) = -10mA to -30mA COUT(x) = 50pF COUT(x) = 50pF Measured on CS Measured on CS 100mV Overdrive on CS, (Note 2) SS = 2.5V Measured on SS Measured on SS 10 0.7 4.5 280 475 MIN 9.0 TYP 9.2 0.44 11 15 10 10 300 600 80 13 0.4 4.2 16 0.1 3.5 320 725 0.6 15 20 MAX UNITS V V ns ns mV mV ns A V V Synchronous Outputs
ELECTRICAL CHARACTERISTICS
Current Limit and Shutdown
Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: Includes leading edge blanking delay, RLEB = 20k, not tested in production. Note 3: FB is driven by a servo loop amplifier to control VCOMP for these tests. Note 4: Set FB to -0.3V, 2.5V and insure that COMP does not phase invert. Note 5: The LTC3723E-1/LTC3723E-2 are guaranteed to meet performance specifications from 0C to 85C. Specifications over the
-40C to 85C operating temperature range are assured by design, characterization and correlation with statistical process controls. Note 6: This IC includes overtemperature protection that is intended to protect the device during momentary overload conditions. Junction temperature will exceed 125C when overtemperature protection is active. Continuous operation above the specified maximum operating junction temperature may impair device reliability.
PI DESCRIPTIO S
VREF (Pin 1/Pin 1): Output of the 5.0V Reference. VREF is capable of supplying up to 18mA to external circuitry. VREF should be decoupled to GND with a 1F ceramic capacitor. SDRB (Pin 2/Pin 2): 50mA Driver for Synchronous Rectifier associated with DRVB. SDRA (Pin 3/Pin 3): 50mA Driver for Synchronous Rectifier associated with DRVA. DRVB (Pin 4/Pin 4): High Speed 1.5A Sink, 1A Source Totem Pole MOSFET Driver. Connect to gate of external push-pull MOSFET with as short a PCB trace as practical to preserve drive signal integrity. A low value resistor connected between DRVA and the MOSFET gate is op-
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(LTC3723-1/LTC3723-2)
tional and will improve the gate drive signal quality if the PCB trace from the driver to the MOSFET cannot be made short. VCC (Pin 5/Pin 5): Supply Voltage Input to the LTC3723-1/ LTC3723-2 and 10.25V Shunt Regulator. The chip is enabled after VCC has risen high enough to allow the VCC shunt regulator to conduct current and the UVLO comparator threshold is exceeded. Once the VCC shunt regulator has turned on, VCC can drop to as low as 6V (typical) and maintain operation. Bypass VCC to GND with a high quality 1F or larger ceramic capacitor to supply the transient currents caused by the high speed switching and capacitive loads presented by the on chip totem pole drivers.
372312i
LTC3723-1/LTC3723-2
PI DESCRIPTIO S
DRVA (Pin 6/Pin 6): High Speed 1.5A Sink, 1A Source Totem Pole MOSFET Driver. Connect to gate of external push-pull MOSFET with as short a PCB trace as practical to preserve drive signal integrity. A low value resistor connected between DRVA and the MOSFET gate is optional and will improve the gate drive signal quality if the PCB trace from the driver to the MOSFET cannot be made short. GND (Pin 7/Pin 7): All circuits in the LTC3723 are referenced to GND. Use of a ground plane is highly recommended. VIN and VREF bypass capacitors must be terminated with a star configuration as close to GND as practical for best performance. CT (Pin 8/Pin 8): Timing Capacitor for the Oscillator. Use a 5% or better low ESR ceramic capacitor for best results. CT ramp amplitude is 2.35V peak-to-peak (typical). DPRG (Pin 9/Pin 12): Programming Input for Push-Pull Dead-Time. Connect a resistor between DPRG and VREF to program the dead-time. The dead-time is approximately equal to (1.30 * 10-12 * RDPRG). The nominal voltage on DPRG is 2V. RAMP (N/A/Pin 9): Input to PWM Comparator for LTC3723-2 Only (Voltage Mode Controller). The voltage on RAMP is internally level shifted by 650mV. CS (Pin 10/Pin 10): Input to Pulse-by-Pulse and Overload Current Limit Comparators, Output of Slope Compensation Circuitry. The pulse-by-pulse comparator has a nominal 300mV threshold, while the overload comparator has a nominal 600mV threshold. An internal switch discharges CS to GND after every timing period. Slope compensation current flows out of CS during the PWM period. An external resistor connected from CS to the external current sense resistor programs the amount of slope compensation. COMP (Pin 11/Pin 11): Error Amplifier Output, Inverting Input to Phase Modulator.
U
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(LTC3723-1/LTC3723-2)
RLEB (Pin 12/N/A): Timing Resistor for Leading Edge Blanking. Use a 10k to 100k resistor connected between RLEB and GND to program from 40ns to 310ns of leading edge blanking of the current sense signal on CS for the LTC3723-1. A 1% tolerance resistor is recommended. The LTC3723-2 has a fixed blanking time of approximately 80ns. The nominal voltage on RLEB is 2V. If leading edge blanking is not required, tie RLEB to VREF to disable. FB (Pin 13/Pin 13): Error Amplifier Inverting Input. This is the voltage feedback input for the LTC3723. The nominal regulation voltage at FB is 1.2V. SS (Pin 14/Pin 14): Soft-Start/Restart Delay Circuitry Timing Capacitor. A capacitor from SS to GND provides a controlled ramp of the current command (LTC3723-1) or duty cycle (LTC3723-2). During overload conditions, SS is discharged to ground initiating a soft-start cycle. SS charging current is approximately 13A. SS will charge up to approximately 5V in normal operation. During a constant overload current fault, SS will oscillate at a low frequency between approximately 0.5V and 4V. UVLO (Pin 15/Pin 15): Input to Program System Turn-On and Turn-Off Voltages. The nominal threshold of the UVLO comparator is 5.0V. UVLO is connected to the main DC system feed through a resistor divider. When the UVLO threshold is exceeded, the LTC3723-1/LTC3723-2 commences a soft-start cycle and a 10A (nominal) current is fed out of UVLO to program the desired amount of system hysteresis. The hysteresis level can be adjusted by changing the resistance of the divider. UVLO can also be used to terminate all switching by pulling UVLO down to less than 4V. An open drain or collector switch can perform this function without changing the system turn on or turn off voltages. SPRG (Pin 16/Pin 16): A resistor is connected between SPRG and GND to set the turn off delay for the synchronous rectifier driver outputs. The nominal voltage on SPRG is 2V.
372312i
5
LTC3723-1/LTC3723-2
TI I G DIAGRA
PWM COMPARATOR (-)
BLOCK DIAGRA S
LTC3723-1 Block Diagram
VCC 5 UVLO 15 VREF 1 CT 8 DPRG 9 SPRG 16
VCC UVLO 10.25V "ON" 6V "OFF" ERROR AMPLIFIER
FB 13
- +
+
5V
1.2V
-
PULSE WIDTH MODULATOR
50k COMP 11 14.9k
+
650mV
-
1A SOURCE Q VREF 13A SS 14 SHUTDOWN CURRENT LIMIT S R S 1A SOURCE FAULT LOGIC 1.5A SINK 4 DRVB Q R Q T Q 1.5A SINK 6 DRVA
+
600mV
-
CS 10 RLEB 12
BLANK
+
300mV
PULSE-BY-PULSE CURRENT LIMIT
-
6
W
PROGRAMMABLE SYNCHRONOUS TURN-OFF DELAY DRVA DRVB PROGRAMMABLE DEAD-TIME SDRA SDRB CURRENT SENSE OR CT RAMP
372312 TD01
W
UW
10A VCC
REF, LDO 1.2V
5V
REF GOOD SYSTEM UVLO VCC GOOD
3 SDRA SYNC RECTIFIER DRIVE LOGIC 2 SDRB
- +
OSCILLATOR
SLOPE COMPENSATOR
7 GND
372312 BD01
372312i
LTC3723-1/LTC3723-2
BLOCK DIAGRA S
LTC3723-2 Block Diagram
VCC 5 UVLO 15 VREF 1 CT 8 DPRG 12 SPRG 16
VCC UVLO 10.25V "ON" 6V "OFF" ERROR AMPLIFIER
FB 13
- +
1.2V
5V
50k COMP 11
+
650mV
-
RAMP 9 Q VREF 13A SS 14 SHUTDOWN CURRENT LIMIT S R S 1A SOURCE FAULT LOGIC 1.5A SINK 4 DRVB Q R Q T Q 1.5A SINK 1A SOURCE 6 DRVA
+
600mV
-
CS 10
BLANK
+
300mV
PULSE-BY-PULSE CURRENT LIMIT
-
W
+ -
10A VCC
REF, LDO 1.2V
5V
REF GOOD SYSTEM UVLO VCC GOOD
3 SDRA SYNC RECTIFIER DRIVE LOGIC 2 SDRB
- +
PULSE WIDTH MODULATOR
OSCILLATOR
SLOPE COMPENSATOR
7 GND
372312 BD02
372312i
7
LTC3723-1/LTC3723-2
OPERATIO
Please refer to the detailed Block Diagrams for this discussion. The LTC3723-1 and LTC3723-2 are synchronous PWM push-pull controllers. The LTC3723-1 operates with peak pulse-by-pulse current mode control while the LTC3723-2 offers voltage mode control operation. They are best suited for moderate to high power isolated power systems where small size and high efficiency are required. The push-pull topology delivers excellent transformer utilization and requires only two low side power MOSFET switches. Both controllers generate 180 out of phase 0% to < 50% duty cycle drive signals on DRVA and DRVB. The external MOSFETs are driven directly by these powerful on-chip drivers. The external MOSFETs typically control opposite primary windings of a centertapped power transformer. The centertap primary winding is connected to the input DC feed. The secondary of the transformer can be configured in different synchronous or nonsynchronous configurations depending on the application needs. The duty ratio is controlled by the voltage on COMP. A switching cycle commences with the falling edge of the internal oscillator clock pulse. The LTC3723-1 attenuates the voltage on COMP and compares it to the current sense signal to terminate the switching cycle. The LTC3723-2 compares the voltage on COMP to a timing ramp to terminate the cycle. The LTC3723-2's CT waveform can be used for this purpose or separate R-C components can be connected to RAMP to generate the timing ramp. If the voltage on CS exceeds 300mV, the present cycle is terminated. If the voltage on CS exceeds 600mV, all switching stops and a soft-start sequence is initiated.
VREF
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The LTC3723-1 / LTC3723-2 also provide drive signals for secondary side synchronous rectifier MOSFETs. Synchronous rectification improves converter efficiency, especially as the output voltages drop. Independent turn-off control of the synchronous rectifiers is provided via SPRG in order to optimize the benefit of the synchronous rectifiers. A resistor from SPRG to GND sets the desired turn off delay. A host of other features including an error amplifier, system UVLO programming, adjustable leading edge blanking, slope compensation and programmable dead-time provide flexibility for a variety of applications. Programming Driver Dead-Time The LTC3723-1/LTC3723-2 controllers include a feature to program the minimum time between the output signals on DRVA and DRVB commonly referred to as the driver dead-time. This function will come into play if the controller is commanded for maximum duty cycle. The dead-time is set with an external resistor connected between DPRG and VREF (see Figure 1). The nominal regulated voltage on DPRG is 2V. The external resistor programs a current which flows into DPRG. The dead-time can be adjusted from 90ns to 300ns with this resistor. The dead-time can also be modulated based on an external current source that feeds current into DPRG. Care must be taken to limit the current fed into DPRG to 350A or less.
RDPRG DPRG
+
V 2V
+
2.5V
-
-
TURN-ON OUTPUT
3722 F01
Figure 1. Delay Timeout Circuitry
372312i
LTC3723-1/LTC3723-2
OPERATIO
Powering the LTC3723-1/LTC3723-2 The LTC3723-1/LTC3723-2 utilize an integrated VCC shunt regulator to serve the dual purposes of limiting the voltage applied to VCC as well as signaling that the chip's bias voltage is sufficient to begin switching operation (under voltage lockout). With its typical 10.2V turn-on voltage and 4.2V UVLO hysteresis, the LTC3723-1/LTC3723-2 is tolerant of loosely regulated input sources such as an auxiliary transformer winding. The VCC shunt is capable of sinking up to 40mA of externally applied current. The UVLO turn-on and turn-off thresholds are derived from an internally trimmed reference making them extremely accurate. In addition, the LTC3723-1/LTC3723-2 exhibits very low (145A typ) start-up current that allows the use of 1/8W to 1/4W trickle charge start-up resistors. The trickle charge resistor should be selected as follows: RSTART(MAX) = VIN(MIN) - 10.7V/250A Adding a small safety margin and choosing standard values yields:
APPLICATION DC/DC Off-Line PFC Preregulator VIN RANGE 36V to 72V 85V to 270VRMS 390VDC RSTART 100k 430k 1.4M
VCC should be bypassed with a 0.1F to 1F multilayer ceramic capacitor to decouple the fast transient currents demanded by the output drivers and a bulk tantalum or electrolytic capacitor to hold up the VCC supply before the bootstrap winding, or an auxiliary regulator circuit takes over. CHOLDUP = (ICC + IDRIVE) * tDELAY/3.8V (minimum UVLO hysteresis)
12V 10% 1.5k 1N5226 3V VIN VBIAS < VUVLO 1N914 RSTART
VCC
Figure 2. Bias Configurations
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Regulated bias supplies as low as 7V can be utilized to provide bias to the LTC3723-1/LTC3723-2. Refer to Figure 2 for various bias supply configurations. Programming Undervoltage Lockout The LTC3723-1/LTC3723-2 provides undervoltage lockout (UVLO) control for the input DC voltage feed to the power converter in addition to the VCC UVLO function described in the preceding section. Input DC feed UVLO is provided with the UVLO pin. A comparator on UVLO compares a divided down input DC feed voltage to the 5V precision reference. When the 5V level is exceeded on UVLO, the SS pin is released and output switching commences. At the same time a 10A current is enabled which flows out of UVLO into the voltage divider connected to UVLO. The amount of DC feed hysteresis provided by this current is: 10A * RTOP, (Figure 3). The system UVLO threshold is: 5V * {(RTOP + RBOTTOM)/RBOTTOM}. If the voltage applied to UVLO is present and greater than 5V prior to the VCC UVLO circuitry activation, then the internal UVLO logic will prevent output switching until the following three conditions are met: (1) VCC UVLO is enabled, (2) VREF is in regulation and (3) UVLO pin is greater than 5V. UVLO can also be used to enable and disable the power converter. An open drain transistor connected to UVLO as shown in Figure 3 provides this capability.
RTOP UVLO ON OFF RBOTTOM
3722 F03
Figure 3. System UVLO Setup
+
1F VCC 1F CHOLD
3722 F02
372312i
9
LTC3723-1/LTC3723-2
OPERATIO
Off-Line Bias Supply Generation If a regulated bias supply is not available to provide VCC voltage to the LTC3723-1/LTC3723-2 and supporting circuitry, one must be generated. Since the power requirement is small, approximately 1W, and the regulation is not critical, a simple open-loop method is usually the easiest and lowest cost approach. One method that works well is to add a winding to the main power transformer, and post regulate the resultant square wave with an L-C filter (see Figure 4a). The advantage of this approach is that it maintains decent regulation as the supply voltage varies, and it does not require full safety isolation from the input winding of the transformer. Some manufacturers include a primary winding for this purpose in their standard product offerings as well. A different approach is to add a winding to the output inductor and peak detect and filter the square wave signal (see Figure 4b). The polarity of this winding is designed so that the positive voltage square wave is produced while the output inductor is freewheeling. An advantage of this technique over the previous is that it does not require a separate filter inductor and since the voltage is derived from the well-regulated output
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voltage, it is also well controlled. One disadvantage is that this winding will require the same safety isolation that is required for the main transformer. Another disadvantage is that a much larger VCC filter capacitor is needed, since it does not generate a voltage as the output is first starting up, or during short-circuit conditions. Programming the LTC3723-1/LTC3723-2 Oscillator The high accuracy LTC3723-1/LTC3723-2 oscillator circuit provides flexibility to program the switching frequency and slope compensation required for current mode control (LTC3723-1). The oscillator circuit produces a 2.35V peak-to-peak amplitude ramp waveform on CT. Typical maximum duty cycles of 49% are possible. The oscillator is capable of operation up to 1MHz by the following equation: CT = 1/(14.8k * FOSC) Note that this is the frequency seen on CT. The output drivers switch at 1/2 of this frequency. Also note that higher switching frequency and added driver dead-time via DPRG will reduce the maximum duty cycle.
VIN RSTART VCC
+
15V* CHOLD
2k 1F
1922 F04a
*OPTIONAL
Figure 4a. Auxiliary Winding Bias Supply
VIN LOUT RSTART ISO BARRIER VOUT
+
1F
CHOLD
VCC
1922 F04b
Figure 4b. Output Inductor Bias Supply
372312i
LTC3723-1/LTC3723-2
OPERATIO
The LTC3723-1 derives a compensating slope current from the oscillator ramp waveform and sources this current out of CS. This function is disabled in the LTC3723-2. The desired level of slope compensation is selected with an external resistor connected between CS and the external current sense resistor, (Figure 5). Current Sensing and Overcurrent Protection Current sensing provides feedback for the current mode control loop and protection from overload conditions. The LTC3723-1/LTC3723-2 are compatible with either resistive sensing or current transformer methods. Internally connected to the LTC3723-1/LTC3723-2 CS pin are two comparators that provide pulse-by-pulse and overcurrent shutdown functions respectively, (Figure 6). The pulse-by-pulse comparator has a 300mV nominal threshold. If the 300mV threshold is exceeded, the PWM cycle is terminated. The overcurrent comparator is set
LTC3723 CT I= V(CT) 33k
Figure 6. Current Sense/Fault Circuitry Detail
372312i
+
UVLO ENABLE
R
+
650mV
-
SQ
-
-
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approximately 2x higher than the pulse-by-pulse level. If the current signal exceeds this level, the PWM cycle is terminated, the soft-start capacitor is quickly discharged and a soft-start cycle is initiated. If the overcurrent condition persists, the LTC3723-1/LTC3723-2 halts PWM operation and waits for the soft-start capacitor to charge up to approximately 4V before a retry is allowed. The softstart capacitor is charged by an internal 13A current source. If the fault condition has not cleared when softstart reaches 4V, the soft-start pin is again discharged and a new cycle is initiated. This is referred to as hiccup mode operation. In normal operation and under most abnormal conditions, the pulse-by-pulse comparator is fast enough to prevent hiccup mode operation. In severe cases, however, with high input voltage, very low RDS(ON) MOSFETs and a shorted output, or with saturating magnetics, the overcurrent comparator provides a means of protecting the power converter.
SWITCH CURRENT CS RSLOPE RCS 33k ADDED SLOPE CURRENT SENSE WAVEFORM
3722 F05
Figure 5. Slope Compensation Circuitry
PULSE BY PULSE CURRENT LIMIT + CS 270mV - PWM
PWM LATCH Q S PWM LOGIC
UVLO ENABLE SQ R
H = SHUTDOWN OUTPUTS
Q
RCS
OVERLOAD CURRENT LIMIT +
4.1V
13A SS
0.4V
CSS
Q
3722 F06
11
LTC3723-1/LTC3723-2
OPERATIO
Leading Edge Blanking The LTC3723-1/LTC3723-2 provides programmable leading edge blanking to prevent nuisance tripping of the current sense circuitry. Leading edge blanking relieves the filtering requirements for the CS pin, greatly improving the response to real overcurrent conditions. It also allows the use of a ground referenced current sense resistor or transformer(s), further simplifying the design. With a single 10k to 100k resistor from RLEB to GND, blanking times of approximately 40ns to 320ns are programmed. If not required, connecting RLEB to VREF can disable leading edge blanking. Keep in mind that the use of leading edge blanking will slightly reduce the linear control range for the pulse width modulator. High Current Drivers The LTC3723-1/LTC3723-2 high current, high speed drivers provide direct drive of external power N-channel MOSFET switches. The drivers swing from rail to rail. Due to the high pulsed current nature of these drivers (1.5A sink, 1A source), care must be taken with the board layout to obtain advertised performance. Bypass VCC with a 1F minimum, low ESR, ESL ceramic capacitor. Connect this capacitor with minimal length PCB leads to both VCC and GND. A ground plane is highly recommended. The driver output pins (DRVA, DRVB) connect to the gates of the external MOSFET switches. The PCB traces making these connections should also be as short as possible to minimize overshoot and undershoot of the drive signal. Synchronous Rectification The LTC3723-1/LTC3723-2 produces the precise timing signals necessary to control secondary side synchronous
SPRG
12
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rectifier MOSFETs on SDRA and SDRB. Synchronous rectifiers are used in place of Schottky or silicon diodes on the secondary side to improve converter efficiency. As MOSFET RDS(ON) levels continue to drop, significant efficiency improvements can be realized with synchronous rectification, provided that the MOSFET switch timing is optimized. Synchronous rectification also provides bipolar output current capability, that is, the ability to sink as well as source current. Programming the Synchronous Rectifier Turn-Off Delay The LTC3723-1/LTC3723-2 controllers include a feature to program the turn-off edge of the secondary side synchronous rectifier MOSFETs relative to the beginning of a new primary side power delivery pulse. This feature provides optimized timing for the synchronous MOSFETs which improves efficiency. At higher load currents it becomes more advantageous to delay the turn-off of the synchronous rectifiers until the transformer core has been reset to begin the new power pulse. This allows for secondary freewheeling current to flow through the synchronous MOSFET channel instead of its body diode. The turn-off delay is programmed with a resistor from SPRG to GND, (Figure 7). The nominal regulated voltage on SPRG is 2V. The external resistor programs a current which flows out of SPRG. The delay can be adjusted from approximately 20ns to 200ns, with resistor values of 10k to 200k. Do not leave SPRG floating. The amount of delay can also be modulated based on an external current source that sinks current out of SPRG. Care must be taken to limit the current out of SPRG to 350A or less.
RSPRG
+
V 2V
+ -
TURN-OFF SYNC OUT
-
3722 F07
Figure 7. Synchronous Delay Circuitry
372312i
D24
D25 1 * * 3 2 * * L6 0.65H +VOUT 3.3V/50A +VOUT
L5 1.3H 100pF 200V 80 1W 100pF 200V
VIN
+VIN
9 10 7 8 11 12
C2 0.82F 100V
80 1W
+
4 10V Si7892DP x3 L4 1mH D12 5 * D14 6 T1 9:9:7:1:1 Q17 Q18 -VOUT 4.7k 6 470pF 4 * D17 5 T2 1.5mH 1:0.5:0.5 220pF D15 5 100 1/4W 3 1 4 7 OUT2 OUT1 8.5V IN2 IN1 GND2 VCC2 VCC1 GND1 LTC1693-1CS8 6 8 2 D26 9.1V 1F Q33 100 D8 D9 4.7 1/4W Si7892DP x3
1F
TYPICAL APPLICATIO
36VIN to 72VIN
C3, C4, C5 0.82F 100V x3 Si7450DP Si7450DP
C32, C33, C34 470F 6.3V x3
-VIN
+
-VOUT -VOUT
C14 68F 20V 0.03 2W 470 * 1 75k * 22 8 0.1F 330pF 3
2k 1/4W
5V
10F
10V 8.5V 10 CS DRVB 1k 4 7 MOC207 47nF 3 V+ 1 2 4 8 6 0.1F 5 5V 33k 68nF 1F C30 2.2nF 100k 8 2 3 1 360 SDRB 3 SDRA 11 LTC3723EGN-1 SS DPRG 14 820 150k 9 1 COMP VREF 4 2
VIN
100 1/4W
6
-VOUT +VOUT +VOUT 787 270 0.022F 0.68F
30k
5
DRVA
VCC
383k
15
UVLO CT SPRG RLEB GND FB 7 13
100pF
8
16
12
1F
10k
COMP RTOP LT1431CS8 COLL REF GND-F GND-S RMID 6 5 7
Q34 2.49k 47 -VOUT -VOUT D27 1k
66.5k
150pF
C2, C3-C5: VITRAMON VJ1812Y824KXBAT C14: AVX TPSE686M020R0150 C30: MURATA DE2E3KH222MB3B C32, C33, C34: SANYO 6TPB470M D8, D9: DIODES INC. MMBD914 D12, D14: BAS21 D15, D17, D27: BAT54 D24, D25: B0540W D26: MMBD5239B L4: COILCRAFT DO1608C-105 L5: SUMIDA CDEP105-1R3MC-50 L6: PULSE PA1294.650 Q17, Q18: ZETEX FMMT718 Q34: FMMT3904 Q33: FZT690B T1: EFD25 TRANSPOWER TTI8796 T2: PULSE PA0297
372312 F08
Figure 8. LTC3723-1 165W, 36VIN to 72VIN to 3.3V/50A Isolated Push-Pull Converter
U
LTC3723-1/LTC3723-2
13
372312i
TYPICAL APPLICATIO
0.03 1W Q17 Q18
LTC3723-1/LTC3723-2
T1 7:6:6:1:1 D8 D9
3.3 1/4W
-VOUT
470 * 1 75k * 330 8 * 5 T2 1.5mH 1:0.5:0.5 3k 1nF D17 20k 0.1F 4 330pF 6 D15 20k
3 470
1nF -VOUT
7
5 OUT1 OUT2 12V 3 1 4 IN2 IN1 GND2 VCC2 VCC1 GND1 LTC1693-1CS8 6 8 2 1F D26 12V 10F
5V
10V 12V 10 CS 1k 4 3 MOC207 47nF 3 V+ 1 2 4 8 1 7 6 0.1F 5 5V 33k 68nF 1F 100k 8 2 360 DRVB SDRB 3 SDRA 11 4 2
VIN
150 1/4W
-VOUT +VOUT +VOUT 787 270 0.022F 0.68F
30k
5
VCC
383k COMP VREF 1 820 150k
LTC3723EGN-1
15
UVLO CT 7 13 14 9
DRVA SPRG RLEB GND FB SS DPRG
100pF
8
6
16
12
68pF
1F
10k
390pF
COMP RTOP LT1431CS8 COLL REF GND-F GND-S RMID 6 5 7
Q34 2.49k 47 -VOUT -VOUT D27 1k
66.5k C30 2.2nF
390
D28
C2, C3-C5: VITRAMON VJ1812Y824KXBAT C14: AVX TPSE686M020R0150 C30: MURATA DE2E3KH222MB3B C32, C33: SANYO 6TPB470M D8, D9: DIODES INC. MMBD914 D12, D14: BAS21 D15, D17, D27, D28: BAT54 D24, D25: B0540W D26: MMBD5242B L4: COILCRAFT DO1608C-105 L5: SUMIDA CDEP105-1R3MC-50 L6: PULSE PA1294.910 Q17, Q18: ZETEX FMMT718 Q34: FMMT3904 T1: PULSE PA0810.007 PLANER T2: PULSE PA0297
372312 F09
Figure 9. LTC3723-1 100W, 36VIN to 72VIN to 3.3V/30A Isolated Forward Converter
U
-VOUT
14
2 7 D24 * D25 4 3 8 10 +VOUT L6 0.85H 5 11 1nF 200V Si7450DP L4 1mH D12 1 * D14 6 Si7892DP x3 Si7892DP x3 C14 68F 20V 10V +VOUT 3.3V/30A * * *
L5 1.3H
VIN
+VIN
C2 0.82F 100V
36VIN to 72VIN
C3, C4, C5 0.82F 100V x3
+
C32, C33 470F 6.3V x2
1F
-VIN
+
372312i
LTC3723-1/LTC3723-2
PACKAGE DESCRIPTIO
.254 MIN
.0165 .0015
RECOMMENDED SOLDER PAD LAYOUT 1 .015 .004 x 45 (0.38 0.10) .007 - .0098 (0.178 - 0.249) .016 - .050 (0.406 - 1.270) NOTE: 1. CONTROLLING DIMENSION: INCHES INCHES 2. DIMENSIONS ARE IN (MILLIMETERS) 3. DRAWING NOT TO SCALE *DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE 0 - 8 TYP .053 - .068 (1.351 - 1.727) 23 4 56 7 8 .004 - .0098 (0.102 - 0.249)
U
GN Package 16-Lead Plastic SSOP (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1641)
.189 - .196* (4.801 - 4.978) 16 15 14 13 12 11 10 9 .045 .005 .009 (0.229) REF .150 - .165 .229 - .244 (5.817 - 6.198) .150 - .157** (3.810 - 3.988) .0250 TYP .008 - .012 (0.203 - 0.305) .0250 (0.635) BSC
GN16 (SSOP) 0502
372312i
15
LTC3723-1/LTC3723-2
RELATED PARTS
PART NUMBER LT1431 LT1681/LT3781 LTC1693-1 LT3804 DESCRIPTION Reference and Opto-Driver Synchronous Forward Controllers Dual MOSFET Gate Drivers Secondary Side Dual Output Controller with Opto Driver COMMENTS Drives Opto-Coupler High Efficiency 2-Switch Forward Control High Speed MOSFET Gate Drivers ZVS Full-Bridge Controllers Regulates Two Secondary Outputs; Optocoupler Feedback Driver and Second Output Synchronous Driver Controller
LTC3722-1/LTC3722-2 Dual Mode Phase Modulated Full-Bridge Controllers
372312i
16
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 q FAX: (408) 434-0507
q
LT/TP 1003 1K * PRINTED IN USA
www.linear.com
(c) LINEAR TECHNOLOGY CORPORATION 2003

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